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SP9841/42
8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC
s Replaces 8 Potentiometers and 8 Op Amps s Operates from Single +5V Supply s 6.3 MHz 2-Quadrant Multiplying Gain Bandwidth s No Signal Inversion s Eight Reference Inputs, Eight Voltage Outputs (SP9841) s Four Reference Inputs, Eight Voltage Outputs (SP9842) s 3-Wire Serial Input s 0.8MHz Data Update Rate s +3.25 Volt Output Swing s Midscale Preset s Low 65 mW Power Dissipation (8mW/DAC) DESCRIPTION... The SP9841 and SP9842 are general purpose octal DACs in a single package. The SP9841 features eight individual reference inputs, while the SP9842 provides four pair of voltage reference inputs. Both parts feature 6.3MHz bandwidth, two-quadrant multiplication, and a three-wire serial interface. Other features include midscale preset, no signal inversion and low power dissipation from a single +5V supply. Devices are available in commercial and industrial temperature ranges.
DAC A
+
VINA VOUTA
8 Data Clock Serial Data Input Serial Data Output SERIAL REGISTER 8 8x8 DAC REGISTER
-
SP9842 Block Diagram
DAC A
+
Preset Load 4 LOGIC 8
8
-
VOUTA VINA/B VOUTB
VINH DAC H 8 VOUTH
Data Clock Serial Data Input Serial Data Output Preset Load 4 LOGIC 8 8 Decoded Address SERIAL REGISTER 8 8x8 DAC REGISTER
+
DAC B 8
-
Decoded Address SP9841
VREF Low
SP9841 Block Diagram
DAC G
+ -
VOUTG VING/H VOUTH
DAC H SP9842
+
8
-
VREF Low
267
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VDD to GND ...................................................................... -0.3V, +7V VINX to GND ............................................................................... VDD VREFL to GND ............................................................................. VDD VOUTX to GND ............................................................................ VDD Short Circuit IOUTX to GND ............................................ Continuous Digital Input & Output Voltage to GND ....................................... VDD Operating Temperature Range Commercial: SP9841K/SP9842K .............................. 0C to +70C Extended Industrial: SP9841B/SP9842B ................ -40C to +85C Maximum Junction Temperature (TJ max) .......................... +150C Storage Temperature ................................................. -65 to 150C Lead Temperature (Soldering, 10 sec) ............................... +300C Package Power Dissipation ................................. (TJ max - TA)/JA Thermal Resistance JA P-DIP .................................................................................. 57C/W SOIC-24 .............................................................................. 70C/W
CAUTION: While all input and output pins have internal protection networks, these parts should be considered ESD (ElectroStatic Discharge) sensitive devices. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed.
SPECIFICATIONS
(VDD = +5V, All VINX= +1.625V, VREFL = 0V, TA = 25 C for commercial-grade parts; TMIN TA = TMAX for industrial-grade parts; specifications apply to all DAC's unless noted otherwise.)
PARAMETER SIGNAL INPUTS Input Voltage Range Input Resistance SP9841 SP9842 Input Capacitance SP9841 SP9842 VREFL Resistance VREFL Capacitance DIGITAL INPUTS Logic High Logic Low Input Current Input Capacitance Input Coding STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Half-Scale Output Voltage Zero-Scale Output Voltage Output Voltage Drift DYNAMIC PERFORMANCE Multiplying Gain Bandwidth Slew Rate Positive Negative Total Harmonic Distortion Output Settling Time Crosstalk Digital Feedthrough Wideband Noise
MIN. 0 5 2.5
TYP.
MAX. 1.625
UNITS V k k
CONDITIONS VREFL = GND, VDD = 4.75V D = 55H; Code Dependent Code Dependent
10 5 19 38 0.75 190 30 60 250
0.375
pF pF k pF V V A pF
All D = ABH; Code Dependent Code Dependent
2.4 0.8 10 8 Binary 8 0.25 0.2 1.625 20 25 6.3 7.9 -8.3 0.005 0.7 60 70 6 42.5
1.600
1.0 1.0 1.650 100
Bits LSB LSB V mV V/C MHz V/s V/s % s dB nVs V rms
Note 1 Note 1 PR = LOW, Sets D = 80H D = 00H PR = LOW, Sets D = 80H VINX = 100 mV p-p+ 1.0V dc Measured 10% to 90% VOUTX = 100mV to +3.1V VOUTX = +3.1V to 100mV VINX = 0.8VDC + 1.4V p-p D= FFH; 1kHz, fLP = 80 kHz 1 LSB Error Band, 8H to 255H Note 2 VREFL = +1.625V, D = 0 to FFH VOUT = 3.25V; 400Hz to 80kHz
4 3.0 -3.0
268
SPECIFICATIONS (continued)
(VDD = +5V, All VINX= +1.625V, VREFL = 0V, TA = 25 C for commercial-grade parts; TMIN TA = TMAX for industrial-grade parts; specifications apply to all DAC's unless noted otherwise.)
PARAMETER DYNAMIC PERFORMANCE SINAD Digital Crosstalk
MIN.
TYP. 85 6
MAX.
UNIT dB nVs
CONDITIONS VINX = 0.8VDC + 1.4V p-p D= FFH; 1kHz, fLP = 80 kHz SP9842 only; measured between adjacent channels of same pair; D = 7FH to 80H RL = 5k; VDD = 4.75V VOUT < 10mV, VINX=1.625V, PR = LOW No Oscillation IOH = -0.4mA IOL = 1.6mA To rated specifications PR = LOW
DAC OUTPUTS Voltage Range Output Current
0 10
15
VDD-1.5
V mA pF V V V mA mW
Capacitive Load 47,000 DIGITAL OUTPUT Logic High 3.5 Logic Low 0.4 POWER REQUIREMENTS Power Supply Range 4.75 5.00 5.25 Positive Supply Current 13 Power Dissipation 65 ENVIRONMENTAL AND MECHANICAL Operating Temperature Range Commercial 0 +70 Industrial -40 +85 Storage Temperature Range -65 +150 Package SP9841N 24-pin Plastic DIP SP9841S 24-pin SOIC SP9842S 20-pin SOIC
C C C
Note 3
Notes: 1
2 3
The op amp limits the linearity for VOUT 100mV. When VREFL is driven above ground such that the output voltage remains above 100mV, then the linearity specifications apply to all codes. For VREFL = GND, VIN = 1.5V, codes 0 through 7 are not included in differential or integral linearity tests. Integral and differential linearity are computed with respect to the best fit straight line through codes 8 through 255. SP9841 is measured between adjacent channels, f = 100kHz; SP9842 is measured between adjacent pairs, f = 100kHz. For plastic DIP packaging of SP9842, please consult factory.
269
Plot 1. Integral Linearity Error versus Code.
Plot 2. Differential Non-linearity Error versus Code.
Plot 3. Integral Linearity Matching; VOUT A through VOUT D.
270
Plot 4. Integral Linearity Matching; VOUT E through VOUT H.
Plot 5. THD versus Frequency.
Plot 6. PSRR versus Frequency.
271
Plot 7. Small Signal Gain versus Frequency.
VDD = 5V VIN = 0.05V to 1.55V VOUT = 0.1V to 3.1V
Plot 8. Full Scale Pulse Response.
VDD = 5V VIN = 0.05V to 1.55V VOUT = 0.1V to 3.1V
Plot 9. Positive Full Scale Settling.
272
VDD = 5V VIN = 0.05V to 1.55V VOUT = 0.1V to 3.1V
Plot 10. Negative Full Scale Settling.
Plot 11. VIN(X) Current versus Code.
Plot 12. IREFL Current Input Current versus Code.
273
Plot 13. Typical Midscale Output versus Temperature.
Plot 14. Supply Current versus Temperature.
Plot 15. Output Short Circuit Current versus VOUT(X).
274
Plot 16. Sink Current at Zero Scale.
Plot 17. Typical VOUTmax versus VDD.
Plot 18. Typical VOUT min versus VDD versus ISINK.
275
Plot 19. Integral Error versus Code versus VDD; VIN(X) = 0.5V.
Plot 20. Integral Error versus Code versus VDD; VIN(X) = 0.6V.
276
a)
b)
c)
d)
Plot 21. Pulse Response -- a) CLOAD = 470pF, RLOAD = 10MOhm; b) CLOAD = 470pF, RLOAD = 1kOhm; c) 50Ohms in series with CLOAD = 470pF; d) RLOAD = 1kOhm, 50Ohms in series with CLOAD = 470pF.
277
a)
b)
c)
d) Plot 22. Pulse Response -- a) CLOAD = 4,700pF; b) CLOAD = 4,700pF, RLOAD = 1kOhm; c) 30 Ohms in series with CLOAD = 4,700pF; d) RLOAD = 1kOhm, 30Ohms in series with CLOAD = 4,700pF.
278
a)
b)
c)
d) Plot 23. Pulse Response -- a) CLOAD = 47,000pF; b) CLOAD = 47,000pF, RLOAD = 1kOhm; c) 15 Ohms in series with CLOAD = 47,000pF; d) RLOAD = 1kOhm, 15 Ohms in series with CLOAD = 47,000pF.
279
a)
b)
c)
d) Plot 24. Pulse Response -- a) CLOAD = 0.47F; b) CLOAD = 0.47F, RLOAD = 1kOhm; c) 8.2 Ohms in series with CLOAD = 0.47F; d) RLOAD = 1kOhm, 8.2 Ohms in series with CLOAD = 0.47F.
280
PINOUT
VOUTC 1 VOUTB 2 VOUTA 3 VINB 4 VINA 5 VREFL 6 PRESETL 7 VINE 8 VINF 9 VOUTE 10 VOUTF 11 VOUTG 12 24 VOUTD 23 VINC 22 VIND 21 VDD VOUTC 1 VOUTB 2 VOUTA 3 VINA/B 4 VREFL 5 PRESETL 6 VINE/F 7 VOUTE 8 VOUTF 9 VOUTG 10 20 VOUTD 19 VINC/D 18 VDD 17 SDI
SP9841
20 SDI 19 18 17 16 15 14 13 GND SDO CLOCK LOADH VINH VING VOUTH
SP9842
16 GND 15 SDO 14 13 12 11 CLOCK LOADH VING/H VOUTH
SP9841 PINOUT Pin 1 -- VOUTC -- DAC C Voltage Output. Pin 2 -- VOUTB -- DAC B Voltage Output. Pin 3 -- VOUTA -- DAC A Voltage Output. Pin 4 -- VINB -- DAC B Reference Voltage Input. Pin 5 -- VINA -- DAC A Reference Voltage Input. Pin 6 -- VREFL -- DAC Reference Voltage Input Low, common to all DACs. Pin 7 -- PRESETL -- Preset Input; active low; all DAC registers forced to 80H. Pin 8 -- VINE -- DAC E Reference Voltage Input. Pin 9 -- VINF -- DAC F Reference Voltage Input. Pin 10 -- VOUTE -- DAC E Voltage Output. Pin 11 -- VOUTF -- DAC F Voltage Output. Pin 12 -- VOUTG -- DAC G Voltage Output. Pin 13 -- VOUTH -- DAC H Voltage Output. Pin 14 -- VING -- DAC G Reference Voltage Input. Pin 15 -- VINH -- DAC H Reference Voltage Input. Pin 16 -- LOADH -- Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin 17 -- CLOCK -- Serial Clock Input; positive- edge triggered.
Pin 18 -- SDO -- Serial Data Output; active totem- pole output. Pin 19 -- GND -- Ground. Pin 20 -- SDI -- Serial Data Input. Pin 21 -- VDD -- Positive 5V Power Supply. Pin 22 -- VIND -- DAC D Reference Voltage Input. Pin 23 -- VINC -- DAC C Reference Voltage Input. Pin 24 -- VOUTD -- DAC D Voltage Output.
SP9842 PINOUT Pin 1 -- VOUTC -- DAC C Voltage Output. Pin 2 -- VOUTB -- DAC B Voltage Output. Pin 3 -- VOUTA -- DAC A Voltage Output. Pin 4 -- VINA/B -- DAC A and B Reference Voltage Input. Pin 5 -- VREFL -- DAC Reference Voltage Input Low, common to all DACs. Pin 6 -- PRESETL -- Preset Input; active low; all DAC registers forced to 80H. Pin 7 -- VINE/F -- DAC E and F Reference Voltage Input. Pin 8 -- VOUTE -- DAC E Voltage Output. Pin 9 -- VOUTF -- DAC F Voltage Output.
281
Pin 10 -- VOUTG -- DACG Voltage Output. Pin 11 -- VOUTH -- DACH Voltage Output. Pin 12 -- VING/H -- DACG and H Reference Voltage Input. Pin 13 -- LOADH -- Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin 14 -- CLOCK -- Serial Clock Input; positive- edge triggered. Pin 15 -- SDO -- Serial Data Output; active totem- pole output. Pin 16 -- GND -- Ground. Pin 17 -- SDI -- Serial Data Input. Pin 18 -- VDD -- Positive 5V Power Supply. Pin 19 -- VINC/D -- DACC and D Reference Voltage Input. Pin 20 -- VOUTD -- DACD Voltage Output.
FEATURES... The SP9841 and SP9842 include eight separate op amp-buffered eight-bit DACs. These can be used to replace up to eight trimpots with eight low-impedance programmable sources. The SP9841 uses eight separate multiplying reference inputs, while the SP9842 provides four pair of multiplying inputs. All of the reference inputs, in either case, are returned to a common voltage reference low pin. The inherent 2X gain from the two-quadrant multiplying reference inputs to the outputs allows the use of AC or DC multiplying reference inputs generated from a single, low supply voltage. Each DAC has its own data register which holds its output state. These data registers are updated from an internal serial-to-parallel shift register which is loaded from a standard 3-wire serial input digital interface. Twelve data bits make up the data word clocked into the serial input register. This data word is decoded such that the first 4 bits determine the address of the DAC register to be loaded and the last 8 bits are the data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in mul-
LAST D0 LSB D1 D2 D3 D4 D5 D6 D7 A0 A1 A2
FIRST A3 MSB
DATA
MSB LSB
ADDRESS
A3 0 0 0 0 0 0 0 0 1 1 . . 1 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 . . . 1 0 0 . . . 1 1
A2 0 0 0 0 1 1 1 1 0 0 . . 1 D2 0 0
A1 0 0 1 1 0 0 1 1 0 0 . . 1 D1 0 0
A0 0 1 0 1 0 1 0 1 0 1 . . 1 D0 0 1
DAC Updated No Operation DACA DACB DACC DACD DACE DACF DACG DACH No Operation . . No operation DAC Output Voltage VOUT = D/128 (VIN - VREFL) + VREF L VREFL 1/128 (VIN - VREFL) + VREF L . . . 127/128 (VIN - VREFL) + VREF L VIN (Preset Value) 129/128 (VIN - VREFL) + VREF L . . . 254/128 (VIN - VREFL) + VREF L 255/128 (VIN - VREFL) + VREF L
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
Table 1. Serial Input Decoded Truth Table
282
tiple DAC applications without additional external decoding logic. The SP9841/9842 consume only 65 mW from a single +5V power supply. The SP9841 is available in 24-pin plastic DIP and SOIC packages. The SP9842 is available in a space-saving 20-pin SOIC package. For applications requiring code-controlled output polarity reversal regardless of the reference input level (i.e. four-quadrant multiplication), please see the SP9840/SP9843 product data sheet.
8 R DAC 1
+ -
VIN VDAC VOUT R
VREFL
VOUT = 2 X VDAC when VREFL = 0V = 2(D/256) X VIN = D/128 X VIN VOUT = D/128 X (VIN - VREFL) +VREFL
Figure 1. DAC and Output Amplifier Circuit
USING THE SP9841/9842 Theory of Operation Each of the eight channels of the SP9841/SP9842 can be used for signal reconstruction, as a programmable dc source, or as a programmable gain/attenuation block, multiplying an ac reference input by factors of 0 to 1.992. The rugged, wideband output amplifiers provide both current sink and source capability for dc applications, even those driving difficult loads. The dc source mode mimics the functionality of a programmable trimpot with the added benefit of a low impedance buffered output. The amplifier's bandwidth and high open-loop gain allow its use in programmable gain applications where even a low distortion, high resolution signal (such as audio) must be gated on and off or gain-controlled over a -42 to +6dB range. Each channel consists of a voltage-output DAC, implemented using CMOS switches and thin-film resistors in a inverted R-2R ladder configuration. Each DAC drives the positive terminal of an op amp
VREFL= 0V D = FFH
configured for a non-inverting gain of 2 using equal value thin-film feedback and gain-setting resistors. Signal ground is the VREFL pin, the common reference input return for the 8 DAC-op amp channels. As shown in Figure 1, the DAC section can be thought of as a potentiometer across VIN(X) to VREFL. When this potentiometer reaches its maximum output value of 255/256 times VIN, the output will be 1+(RFB/RGAIN) or 2 times the value of VDAC (actually up to 1.9921875 times the input voltage, with VREFL tied to ground). When the potentiometer is at its minimum value of 0/ 256, the output will try to be 0V, again assuming VREFL is tied to ground. The true relation between the dc levels at the VIN pin, VREFL and the output can be described as:
VOUT = ((1 + RFB/RG) * (Data/256) * (VIN - VREFL)) + VREFL where Data is programmable from 0 to 255, and RFB = RG.
3.0
VOUT(X) (Volts)
3.0
VOUT(X) (Volts)
VREFL= 1.5V
2.5 2.0 1.5 1.0 0.5 0 0
2.5 2.0 D = 00H 80 H 1.0 D = H FF 0.5 = D 0 0.75 1.5 VIN(X) (Volts) 1.5
D = 80H
D = 00H 0.5 1.0 VIN(X) (Volts) 1.5
b)
2.25
a)
Figure 2. a) Single-Quadrant, and b) Two-Quadrant Operation
283
When VREFL is tied to ground, this expression reduces to:
VOUT = (Data/128) *VIN
Multiplication of Input Voltages While both the SP9841 and SP9842 are capable of two-quadrant multiplication, this terminology is not very precise when describing a system which runs from a single positive supply. Traditionally, the quadrants have been defined with respect to 0V. A two- quadrant multiplying DAC could produce negative output voltages only if a negative voltage reference were applied. A four-quadrant device could also produce a code-controlled negative output from a positive reference, or a code-controlled positive output from a negative reference. If ground is used to delineate the quadrants, then the SP9841/SP9842 should be considered single-quadrant multiplying devices, as their output op amps cannot produce voltages below ground. In reality, it is possible to define a dc voltage as a signal ground in a single supply system. If the DAC's VREFL pin is driven to the voltage chosen as pseudoground, then each voltage output will exhibit 2-quadrant behavior with respect to pseudoground; that is the output voltage will enter the quadrant below the pseudoground only when the reference input voltage goes below pseudoground. This mode of operation is useful when implementing programmable gain/attenuator sections, especially when the input signal is bipolar with respect to pseudoground, or is ac- coupled into the VIN(X) pin. When VREFL is tied to power supply ground, only output voltages greater
VDD = 4.75V minimum; VOUTMAX < +3.25V 3.0 2.5
VIN(X) (Volts)
than VREFL are possible, and the device performs single-quadrant multiplication, much like a buffered programmable trimpot across a single supply. Figures 2a and 2b show single-quadrant and 2-quadrant performance of the SP9841/SP9842. Applications which require 4-quadrant operation with respect to pseudoground should use the SIPEX SP9840 or SP9843 4-quadrant multiplying DACs. The choice of voltage to use for the pseudoground is limited by the legal voltage swing at the op amp output. The op amp exhibits excellent linearity for output voltages between, conservatively, 100mV and VDD - 1.5V. The op amp BiCMOS output stage consists of an npn follower loaded by an NMOS common sourced to ground. This circuit exhibits wide bandwidth and can source large currents, while retaining the capability of driving the output to voltages close to ground. At output voltages below 25mV, feedback forces some op amp internal nodes toward the supply rails. The NMOS pull-down device gets driven hard and the NMOS device enters the linear range -- it begins to function in the same manner as a 50 ohm resistor. In reality, the wideband amplifier output stage sinks some internal quiescent current even when driving the output towards ground. This sunk current drops across the output stage NMOS transistor ON-resistance and internal routing resistance to provide a minimum output voltage, below which the amplifier cannot drive. This minimum voltage is in the 15 to 25mV range. It varies within a package with each op amp's offset voltage and biasing variations. If an input voltage lower than this minimum, such as code 0 or 1, when VREFL is ground,
VDD = 4.75V minimum; VOUTMAX >100mV 3.0 2.5
VIN(X) (Volts)
2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0
2.0 1.5 1.0 0.5 0 0
b)
0.5
1.0
1.5
2.0
2.5
3.0
a)
VREFL (Volts)
VREFL (Volts)
Figure 3. Reference Voltages a) Normal Operation; b) Maximum Linearity Near Code 1
284
is requested, feedback within the op amp circuit will force internal nodes to the rails, while the output will remain saturated near this minimum value. Non-saturated monotonic behavior returns between 25mV and 100mV at the output, but full open loop gain and linearity are not apparent until the output voltage is nearly 100mV above the negative supply. Applications which require good linearity for codes near zero should drive the VREFL input at least 100mV above the ground pin, as this insures that the output voltage will not go below 100mV for any legal input voltage. Two-quadrant applications (programmable gain/attenuator) usually bias VREFL up at system pseudoground, well above this saturation region, and therefore maintain linearity even at high attenuations (i.e. at code 1). The allowable, useful values of VIN(X) and VREFL are limited if a legal output value is to be expected for all input codes. At maximum gain (DAC code 255) VOUT is approximately equal to 2VIN(X) - VREFL. By solving this equation twice, once with VOUT set to 0V, and then again with Vout set to VDD-1.5V, the chart of Figure 3a results. This chart can be used to find the maximal VIN(X) voltage excursions for any given voltage driven into VREFL. The upper line plots the maximum voltage at VIN(X) and the lower line plots the minimum voltage at VIN(X) at each value of VREFL drive. Normal operation would be for VIN(X) anywhere between the two lines. For example, assume a 4.75V supply voltage, and that the DAC code is set to 255. If VREFL is driven to 1.6V, VIN(X) below 0.8V would require the output amplifier to swing below ground. VIN(X) above 2.425V would require output voltages greater than VDD - 1.5V, or 3.25V. Figure 3b shows the limits on VIN when the minimum VOUT is constrained to be greater than 100mV, for extremely linear operation, even at DAC code 1. In this case, the lower line is 50mV above its position in Figure 3a, except that below VREFL = 100mV, the minimum input voltage stays at 100mV. It should be noted that VIN(X) can always be driven to or slightly beyond the supply rails without harm. Under such circumstances, the DAC code can always be set to provide sufficient attenuation to get an undistorted output. Driving the Reference Inputs The VIN inputs exhibit a code-dependent input resistance, as shown in the specifications. In general, these
inputs should be driven by an amplifier capable of handling the specified load resistance and capacitance. The reference inputs are useful for both ac and dc input sources. However, series resistance into these pins will degrade the linearity of the DAC. A series resistance of 50 Ohms can cause up to 0.5LSB of additional integral linearity degradation for codes near full scale, due to the code-dependent input current dropping across this error resistance. AC- coupled applications should use the largest capacitor value (lowest series resistance) which is practical, or, use an external buffer to drive the inputs. The DAC switches function in a break-before-make manner in order to minimize current spikes at the reference inputs. As previously noted, the reference inputs can withstand driving voltages slightly beyond the power supply rails without harm. The gain of 2 at the op amps limits the choice of VIN/VREFL combinations if clipping is to be avoided at the higher codes. Output Considerations Each DAC output amplifier can easily drive 1Kohm loads in parallel with 15pF at its rated slew rate. The unique BiCMOS amplifier design also ensures stability into heavily capacitive loads -- up to 47,000pF. Under these conditions, the slew rate will be limited by the instantaneous current available for charging the capacitance -- the slew rate will be severely degraded, and some damped ringing will occur. Especially under heavy capacitive loading, a large, low impedance local bypass capacitor will be required. A 0.047F ceramic in parallel with a low-ESR 2.2 to 10Ftantalumarerecommendedforworst-caseloads. The amplifier outputs can withstand momentary shorts to VDD or ground. Continuous short circuit operation can result in thermally induced damage, and should be avoided. If the input reference voltage is reduced to 0.6V, then both the amplifier and DAC are functional at room temperature at supply voltages as low as 2.5V. At VDD = 2.7V, power dissipation is 9.3mW typical, with the serial clock at 4MHz, or 7.0mW typical with the serial clock gated off. Interfacing to the SP9841/SP9842 A simple serial interface, similar to that used in a 74HC594 shift-register with output latch, has been implemented in these products. A serial clock is used 285
PRESET
1 0
tPR tS 1 LSB ERROR BAND
A3 A2 A1 A0 D7 D6 D 5 D 4 D 3 D2 D1 D0
VOUT (FFH) (08H)
SDI 1 0 1 0 1 0
CLOCK LOAD
VOUTFS 0
SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; VIN(X) = 1.5V; VREFL = 0V) SERIAL 1 DATA IN 0 SERIAL 1 DATA OUT 0 CLOCK LOAD 1 0 1 0 tCH tCL AX or DX tDS tDH tPD tCLKD tLD tS 1 LSB ERROR BAND tLDCK
VOUT (FFH) (08H)
CHARACTERISTICS
(Typical @ 25C with VDD = +5V unless otherwise noted.)
PARAMETER Input Clock Pulse Width (tCH, tCL) Data Setup Time (tDS) Data Hold Time (tDH) CLK to SDO Propagation Delay (tPD) DAC Register Load Pulse Width (tLD) Preset Pulse Width (tPR) Clock Edge to Load Time (tCKLD) Load Edge to Next Clock Edge(tLDCK) Figure 4. Timing.
MIN. 50 30 20 50 50 30
TYP.
MAX.
100
60
UNIT ns ns ns ns ns ns ns ns
CONDITIONS
SDI X Data X X
CLK L
LOADH L L
PRESETL H H L H
LOGIC OPERATION No Change Shift In One Bit from SDI Shift Out 12-clock delayed data at SDO All DAC Registers Preset to 80H (Note 1) Load Serial Register Data into DAC(X) Register
X L
X H
Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high. Table 2. Logic Control Input Truth Table.
286
to strobe serial data into a 12-stage shift-register at each rising clock edge. The first four serial bits contain the address of the DAC to be updated, MSB first. The next 8 bits contain the binary value to be loaded into the desired DAC, again MSB first. After the 12th serial bit is clocked in, the LOADH line can be strobed to latch the 8 bits of data into the data holding register for the desired DAC. The address bits feed a decoding network which steers the LOADH pulse to the clock input of the desired DAC data holding register. The output of the 12th shift-register is also buffered and brought out as the SERIAL DATA OUT (SDO), which can be used to cascade multiple devices, or for data verification purposes. The address field is set up such that DAC A is addressed at 0001 (binary). Address 0000(binary) will not affect the operation of any channel, as this combination is easily generated inadvertently at power-up. Other no-operation addresses exist at 1001(binary) through 1111(binary). Another use for no-operation addresses is to mask off updates of any DAC channel in a multiple-part system with cascaded serial inputs and outputs. By sending a valid address and data only to the desired channel, it is possible to simplify the system hardware by driving the LOADH pin at each part in parallel from a single source. Table 1 shows a register-level diagram of the addresses, data, and the resulting operation. A fourth control pin, PRESETL, can be used to simultaneously preset all DAC data holding registers to their mid-scale (80H) values. This will asynchronously force all DAC outputs to buffer the voltages at their respective inputs to their outputs with unity gain. This feature is useful at power-up, as a simple resistor to the supply and capacitor to ground can insure that all DAC outputs start at a known voltage. It can also be used to implement stand-alone (non-programmed) applications, such as a unity gain octal cable driver. Table 2 summarizes the operation of the four digital control inputs. The four digital control input pins have been designed to accept TTL (0.8V to 2.0V minimum) or full 5V CMOS input levels. Timing information is shown in Figure 4. Serial data is fully clocked into the shift-register after 12 clock rising edges, subject to the described setup and hold times. After the shift-register data is valid, the LOADH line can be pulsed high to load data into the desired
DAC data register, which switches the DAC to the new input code. The serial clock input should not see a rising edge while the LOADH pulse is high in order to prevent shift-register data from corruption during data register loading. The serial clock and data input pins are designed to be compatibleasslavesunder NationalSemiconductor's MicrowireTM and MicrowirePlusTM protocols and under Motorola's SPITM and QSPITM protocols. In some micro-controllers, the interface is completed by programming a bit in a general-purpose I/O port as a level, used to strobe the LOADH line at the DACs. This is done in a manner similar to that used for generating a CS signal, which is necessary when driving some other MicrowireTM peripherals. Low Voltage Operation At nominal VDD, the CMOS switches used in the DAC obtain sufficient drive to maintain an ONresistance much lower than the thin-film resistors. This keeps the non-linear voltage-dependent portion of their ON-resistances low, and guarantees both excellent DAC linearity versus code, and low-distortion multiplication of large-swinging AC inputs. The devices in the op amp also receive sufficient drive to guarantee the specified bandwidth and output drive current. However, all circuits within the DACs are quite "functional" at very low values of VDD. By reducing the reference voltages such that the maximum VOUT is near the target of VDD-1.5V, the DACs will provide better than 0.5LSB typical integral performance for DC output voltages between 100mV and VDD-1.5V. Reducing the reference voltage actually aids the linearity of the DACs, even at nominal VDD. This occurs because the NMOS half of the CMOS switches are more fully utilized at reference voltages closer to ground, thus further reducing the ON-resistance of the switches. Reference input currents are proportional to the reference voltages and will also decrease with the reference voltages. Plot 19 shows typical DC output linearity for VIN(X) set to 0.5V, with VDD at 2.5, and then 3.5V. Note that at 3.5V, the linearity is actually much better than the 0.25LSB typical performance at VIN(X) = 1.625V and VDD = 5V. Similarly, Plot 20 shows that this performance level persists for VDD = 4.5V and 5.5V, with VIN(X) set to 0.6V. The price paid for low voltage operation is in op amp gain, bandwidth and es- pecially current sinking at the DAC output. Plots 17 287
+5V
RPULLUP 1.5kOhms
1/8 of SP9841
45F* 1.22V ICL8069 + -
DCOUT
(*Optional Noise Reduction)
3
DCOUT = 20mV to +2.44V for DATA = 00H to FFH. At PRESET, DCOUT = +1.22V
Figure 5. Inexpensive DC Source.
through 19 show that for lower output current values less than 1 mA, the SP9841/9842 can be used effectively even with VDD in the range of 2.7 to 3.3V. Application Circuits Figure 5 shows an inexpensive single-quadrant DC source for generating voltages from near ground to near 2.44V. When using a two-terminal reference, the pull-up resistor should be chosen so that the minimum input resistance of 5kOhms at each VIN(X) can be driven at the lowest expected VDD. At VDD = 4.75V, and VREFL = 1.25V, each input to be driven needs 0.248mA, and the regulator needs 0.1mA to stay well regulated. Thus, to drive all eight inputs, RPULLUP should be chosen to supply at least 2mA. To
operate at 4.75V, 1.75kOhms is required; the 1.5kOhms shown will suffice even if its value is 5% high. To drive a single input, a 10kOhm value could be used. In order to reduce reference and supply generated noise, an optional capacitor of 1 to 100F bypasses the reference. Figure 6 shows a circuit which generates DC voltages roughly symmetric with respect to 2.446V. Two bandgap references are stacked to first drive VREFL to 1.223V, and the input to 2.446V. The pull-up resistor value should again be scaled for worst-case loading -- in order to drive all eight inputs at 4.75V, a value of 620 Ohms is required. At fullscale, the DAC output is near 3.65V. While typical units will source 5mA at an output voltage
+5V
2kOhm +2.44V 45F* 1.22V ICL8069 +1.22V 1.22V ICL8069
1/8 of SP9841
+ -
DCOUT
45F*
3
DCOUT = +1.22V to +3.66V for DATA = 00H to FFH. At PRESET, DCOUT = +2.44V
(*Optional Noise Reduction)
Figure 6. Pseudo Bipolar Source Generates Voltages Above and Below 2.44V.
288
+1.8V R1 10K VI 45F* R2 4.75K
1/8 of SP9841
+ -
OP-90
+ - + 1.22V -
DCOUT
ICL8069
R3 1.2K
3 DCOUT = 20mV to +3.6V for DATA = 00H to FFH. At PRESET, DCOUT = +1.8V
(*Optional Noise Reduction)
Figure 7. Generating Programmable DC Voltages.
of 3.75V while running from a 4.75V supply, this behavior is not tested in device production. If maximum linearity is required near the 3.66V fullscale voltage, then output loading should be kept under 1mA. Figure 7 uses a 1.8V reference to provide an output voltage range from near ground to almost 3.6V. The external micropower reference uses a bandgap in a bootstrapped configuration, which guarantees excellent supply rejection. Voltage at V1 is set by
1.223
R2 (R1 + R2)
VOUT is 1.223V +V1. R3 is used to set the quiescent current through the bandgap, I=V1/R3. The op amp will easily drive one to all eight inputs.
Figure 8 shows a non-programmed standalone application. By tying PRESETL to ground, all channels are permanently set to unity gain. While preset, the input impedance at each input is set to 40kOhms nominal (20kOhms minimum), which minimizes required input current drive. The TL431 reference is programmed by resistors R1 and R2 for 3.3V. R3 is chosen to provide at least 165A for each input driven, plus 0.5mA for the reference at the minimum supply value to be considered. In the Figure, the 560 Ohms shown will drive all eight inputs. The excellent capacitive load capability of the output amplifiers handles any value of capacitive bypass loads without oscillation; however, to minimize ringing at powerup, load capacitance can be chosen to be greater than 0.1F or less than 1,000pF.
+5V DIGIN
AC04 560 32K
2.5V
1/8 of SP9841
+ - PRESET + -
DCOUT
100K
TL431
DIGIN 0 1
DCOUT 3.3V 0V Eight independent 3.3V @ 10mA supplies with logic-level controlled shutdown.
Figure 8. Generating Up to Eight (8) 3.3V @ 10mA DC Supplies with Logic-Level Controlled Shutdown (Non-Programmed).
289
+12V
10F
In
LM317 Out Adjust
R1 499Ohms
VOUT
10kOhms
VDD 1/8 of SP9841
+ - R4 681Ohms
R2 1kOhms
ICL8069 1.22V
V A
R3 511Ohms
3 VOUT = 4.5V TO 5.5V at 1Amp for DATA = 00H to FFH. At PRESET, VOUT = 5.0V
Figure 9. Programmable 1Amp Power Source.
Figure 9 shows a DAC channel controlling the output voltage of an LM317 voltage regulator. By programming the code, the DAC changes its own supply voltage. This circuit can be modified for wider output voltage ranges by reducing the value of R4. However, the circuit as shown requires the DAC to sink 1mA to the negative rail at code 0 at its lowest VDD, at which point the output voltage is 62mV. Thus, programming codes 0 through 5 will do little to influence the output. If R4 is replaced with a short circuit, useful operation would be between 3.9V and 6.15V output; however, the DAC output must then sink 2.5mA at VDD = 3.9V, which results in a minimum DAC output voltage of
around 150mV. Codes above 17 will then provide equally spaced output voltage increments. Figure 10 shows how the gain of an external non- inverting op amp can be programmed. RF and RG are chosen for nominal gain. RTRIMRANGE is then ratioed to RF to provide the desired range of gain trim. A wide gain grange is achievable -- for example, with RF = 11kOhms,RG =1kOhmsandRTRIMRANGE =2.74kOhms, gain would be programmed linearly from 8 to just under 16. The OP-491 shown in Figure 10 is capable for
+5V
2.2F 1VP-P
+5V
1/4 of OP-491 VREFL
+ - RGAIN 2.5kOhms RF 10kOhms RTRIMRANGE 20kOhms
SIG OUT
VDD 1/8 of SP9841
RIBIAS 50kOhms + -
VREFL = Up to VDD/2
AV = 1 +
RF D RF , D = 0 to 255 + 1 - RG 128 RTRIMRANGE
(2.5V nominal for rail-to-rail output at SIG OUT)
3
Set RTRIMRANGE for desired gain-trim range. For RTRIMRANGE = 20kOhms: Code 0, AV = +5.5 Code 128, AV = +5.0 Code 255, AV = +4.51
Figure 10. Adjustable Gain of External Non-Inverting Opamp Circuit; VOUT = Rail-to-rail.
290
rail-to-rail output swing. In order to obtain this performance, VREFL must be externally driven to VDD/2, perhaps by use of the circuit of Figure 11. At VREFL near 2.5V and VDD = 4.75V, the typical positive output headroom at the DAC is limited to 1.15V above 2.5V, so that this circuit is useful for rail-to-rail outputs for gains higher than 4.35 (i.e. 1.15VPP maximum input). Note that
VINH 1/8 of SP9841
+ -
while an AC-coupled input is shown, this circuit is just as useful for DC-coupled inputs which are generated with respect to the VREFL pseudoground voltage. RIBIAS is used for the AC-coupled circuit for opamp bias current return when the DAC is programmed to code 0, as no current flows into VIN(X) at code 0. Figure 11 shows a minimal parts count method
VOUTH At PRESET, VOUT = 1.3V (not well-regulated) 1/8 of SP9841
+ -
3 VINB
Load code 112 for 1.4VOUT = VREFL 96 for 1.6VOUT = VREFL 70 for 2.2VOUT = VREFL VOUTB
3 VINA 1/8 of SP9841
+ -
VREFL 3
VOUTA
ICL8069 + - 301Ohm
RISRC 2kOhm
45F* 1.22V *(Optional Noise Reduction) +5V
The usable range for the bootstrapped VREFL circuit is 1.4 to 2.4VOUT at VDD = 5V, RISRC = 2kOhms. To increase the upper usable limit, decrease value of RISRC. Figure 11. Programmable, Bootstrapped, 1.4V to 2.2V VREFL Drive.
291
of generating a programmable pseudoground voltage at the VREFL terminal. A pseudoground is very useful if any channels are to be used in AC- multiplying applications. In such applications, the pseudoground will set the DC offset of the output signal. The voltage output of this circuit as the code is decreased is non-linear because the DAC bootstraps the increased output voltage by a larger fraction at each code. It is really meant to be programmed only over a range of codes between 104 and perhaps 60. It does exhibit a fairly well-defined output, even if non-intentional codes are programmed. For codes above 112, the output stage resembles a 50 Ohm resistor to ground, and the VREFL output will be near 1.3V, depending upon the loading at the other VIN(X) inputs. For codes below 60, the
output voltage will continue to rise until limited by available current through RISRC. Note that RISRC supplies the actual current into VREFL, and must be chosen in order to supply enough current for all channels, especially if any of the other eight inputs are to be grounded. A plot of VREFL versus code is shown with the Figure, for all other inputs either grounded or tied to the supply. Figure 12 shows a programmable gain/attenuator section using the programmable VREFL drive. The VREFL of each DAC is actually internally connected. When the optional 45F noise reduction capacitor is included, this circuit is capable of 86dB of SNR and 74 to 84dB of SINAD at 1kHz, depending on the pro-
VINB
0.75V 2.2F
1/8 of SP9841
+ -
VREFL
VOUTB
VINA
1/8 of SP9841
+ -
VREFL 3
RISRC 2kOhm 45F* +5V
VOUTA
ICL8069 + - 301
1.22V
*(Optional Noise Reduction)
Load DACA with code 90; sets VREFL =1.7V. Then, load DACB with desired gain: code 255 = +6dB code 128 = 0dB code 64 = -6dB code 1 = -42dB code 0 = -70dB
Figure 12. AC-Coupled, Programmable Gain/Attenuator with Bootstrapped Programmable Output DC Offset (VREFL Drive).
292
grammed gain. Please refer to the THD versus Frequency plot, which was generated by terminating a 600 Ohm source with 150 Ohms to ground, then into this circuit. For the best gain linearity versus code, use the largest (lowest series impedance) coupling capacitor available, or externally buffer the input. Figure 13 shows an external op amp with an inverting programmable gain. In this circuit the maximum output swing at the DAC occurs at the maximum circuit gain. Thus, the headroom restriction at the DAC output applies at the maximum gain, which, for rail-to-rail outputs (VREFL = 2.5V or VDD/2) should be greater than 4.3. By making the programmable gain range large, this circuit can be used to provide rail-to-rail outputs even at the lower gains. This circuit has been ratioed to provide exact integer gain increments for every increase in 25 codes, over the range of -1 to -11. This large range of gain comes at a slight cost -- the output offset of the DAC amplifier will be gained up by -5.12 times at SIG OUT. If this is a problem, a second DAC
channel can be set up with a programmable DC offset adjustment with its output summed through a large resistor into the OP-491 inverting terminal. Note that when RTRIMRANGE is set up for only unity gain change range as in Figure 12, only -0.5 times the DAC output offset will appear at SIG OUT. Another application for the circuits of both Figure 10 and 13 could be to force precise gains from circuits made from imprecise resistors. By restricting the programmable gain range to 2% (by setting RTRIMRANGE to be 100 times RF), the resistors could be 1% values and the programmable gain resolution would increase to better than 12-bits (0.0156%). In this case, only 1% of the DAC output offset voltage would appear at SIG OUT. Figure 14 shows a window comparator and two channels of programmable-gain input. While the input signal is shown as AC-coupled, DC signals of up to rail-to-rail amplitude could be measured by setting the attenuation at the signal
VREFL +5V 2.2F 1.25VP-P
+5V RGAIN 7.68kOhms RF 7.68kOhms RTRIMRANGE 1.5kOhms + -
1/4 of OP-491 SIG OUT
VDD 1/8 of SP9841
+ -
VREFL = Up to VDD/2 3
AV = -
RF D RF - , D = 0 to 255 RG 128 RTRIMRANGE
Set RTRIMRANGE for desired gain-trim range. For RTRIMRANGE = 1.5kOhms: Code 0, AV = -1 Code 25, AV = -2 Code 75, AV = -4 Code 175, AV = -8 Code 225, AV = -10 Code 250, AV = -11 Gain resolution = 4%
Figure 13. Adjustable Gain of External Inverting Opamp Circuit, VOUT = Rail-to-Rail.
293
294
VHI Compare: 1.67V < VOUT < 3.33V for DATA = 0H to FFH. At PRESET, VOUT = 2.5V +5V
360 "Error" LED + -
+5V
10K + - + - VREF LOW = 1.67V
2.5V VHI Compare
VHI = 2.5V
10K
OP-290 V LOW =
10K + - + - 0.83V
VLO Compare
+ -
1/2 of LM339 SIG 1 0.75V
1.0F + - Any DC voltage
SIG1OUT
499
MUXED (or mixed!) signal SIG2OUT
+ - 499
SIG 2 0.75V
1.0F Any DC voltage
1/2 of SP9841 3 VLOW Compare: 1.67V < VOUT < 0V for DATA = 0H to FFH. At PRESET, VOUT = 0.83V SIG1OUT : Gain = 0 to 2x for 0.75VIN 0.17V < VOUT < 3.17V at maximum gain for DATA = 0H to FFH. At PRESET, Gain = 1x.
Figure 14. Two-Channel Multiplexed Window Comparator with Programmable Gain and Limits.
input DACs to the proper code. The LM339 does not really drive the LED to full illumination, due to limited output current, but a pull-up resistor alone will yield a functional TTL error signal. External op amps could use the VREFL voltage as pseudoground. The outputs of the two signal DACs must be isolated with resistors if the two signals are to be multiplexed. This will reduce the signal gain to 255/256 maximum, due to the resistive divider created at the comparator input. If only a single channel was to be window-compared, then the maximum gain to the comparator would be the usual 255/128. Figure 15 shows the schematic of an evaluation board, which can be used with an IBM-compatible (XT or AT) computer and the simple QuickBasic routine of Figure 16 to load each DAC channel with its desired code. A straight- through 25-pin cable can be used, or the board can be plugged directly into the back of the PC. Data is first latched into each 'HC165 parallel- to-serial converter. Then a small state machine is initiated by strobing INI. It clocks the latched data into the serial data input and strobes the LOADH input at the DAC. A pair of banana jacks is used for applying VDD from an external supply. A trimpot-adjustable voltage reference is tied to all eight DAC inputs. On the evaluation board, jumpers will allow this reference to drive any VIN(X) input or the VREFL pin. The other three op amps in the quad OP-491 are available
for breadboarding circuits, such as in Figures 1 through 14. If the reference voltage is adjusted down to 0.5V, the DAC and the board should function with VDD as low as 2.5V. Driving Capacitive Loads Unlike many other products, the SP9841/9842 will not oscillate under purely capacitive loading. However, fullscale step outputs will show overshoot and ringing of up to 40% at worst- case purely capacitive loading (between 1,000 and 10,000pF). Figures 17 through 20 show near fullscale steps under capacitive loads of between 470pF and 0.47F. For capacitance up to 10,000pF, the addition of a resistive load to ground at the op amp output will decrease settling times without adversely affecting the positive-going slew rate. For higher capacitances, this settling time enhancement comes at the expense of positive slew rate, as not all instantaneous current can be used to charge the capacitor. For all values of capacitive load, settling time can be dramatically reduced by adding a small resistor in series with the DAC outputs. Such series resistors will degrade the current sinking ability at the DAC outputs for voltages near ground; while the DACs typically sink 2mA at VDD =5V at VOUT = 110mV, the addition of a 50Ohm resistor would require 210mV after the resistor to sink 2mA. Large capacitances require lower values of series resistance in order to obtain critical damping.
295
296
D0 D1 D2 1 VDD 5 Q CLK CLKN TEST POINTS 6 P5V Q CLR D 2 1 3 PR P5V 1 VOUTC 2 VOUTB 3 VOUTA 4 VINA 5 VINB 6 VREFL 1 LOADL VDD MR 9 SPE TC 10 TE PE CLK P0 P1 P2 P3 Q1 Q2 Q0 14 13 12 Q3 11 R3 1.5KOHM P5V 7 CLK 3 4 5 6 11 12 11 CLK D 8 Q CLR 12 13 PR CLK D 8 Q CLR Q 9 2 15 DACLD PWRUPL 7 PRE 8 VINE 9 VINF 10 VOUTE 11 VOUTF 12 VOUTG 4 2 SH/LD VDD 16 CLK CLK-IH 15 D 14 C 13 B 12 D3 D4 D5 D6 D7 (MSB) A 11 SI 10 SO PWRUPL 9 R1 49.9KOHM 8 GND 3E 4F P5V VOUTD 24 VINC 23 VIND 22 VDD 21 SDI 20 GND 19 SDO 18 CLK 17 LD 16 VINH 15 VING 14 VOUTH 13
DATA
PC PRINTER PORT
C9 0.1F
S1 U6B
1
STR
2
D0
3
D1
5G 6 H 7 SON
4
D2
5 1 CLKN ADDR MSB ADDR2 ADDR1 ADDR LSB 3E 4F D 14 C 13 B 12 A 11 2 SH/LD VDD 16 CLK CLK-IH 15
D3
U1 ADDRESS
C8 0.1F P5V
6
D4
GCLK
7
D5
8
D6
9
D7
14
ALF
16
INI
SP9841
18 8 GND SI 10 SO 9
GND
5G 6 H 7 SON
U2 U4A
13 PR Q 10 9
U7
R4 1.5KOHM R2 2KOHM U8 ICL8069 P5V C12 10F
C13 3PF R5 3KOHM
A1
OUTD INDIND+ VC10 0.1F INC+ INCOUTC R6 10KOHM
R7 14 10KOHM 13 12 11 10 9 8 R8 10KOHM 1 OUTA 2 INA3 INA+
P5V P5V 4 PR CLK D 6 Q 13 CLR 12 11 Q 3 2 1 5 10 P5V
J1
10F C11
Figure 15. Evaluation Board -- Loads SP9841/9842 from IBM PC Parallel Port
U6A
4 V+ 5 INB+ 6 INB7 OUTB
CLK CTRL0
U3A
U3B
P5V 14 VDD OUT 8 5 4 9
C5 0.1F
CLK 10
NOTE: 1. ALL DIGITAL IC'S BYPASSED WITH 0.1FTO GROUND 2. THREE UNCOMMITTED OP AMPS IN THE OP-491 PACKAGE ARE AVAILABLE FOR USER APPLICATIONS.
U5
GND 7
6
U4B
DACLD 2
8
U4C
1 3
CLKN
U1, U2 -- 74HC165 U3, U6 -- 74FC74 U4 -- 74HC02 U5 -- DALE X0-438-8.0, 8MHZ OSCILLATOR U7 -- 74HC161 U8 -- ICL8069 A1 -- OP-491 C1 - C10 -- 0.1F CERAMIC C11, C12 -- 10F/30V C13 -- 3PF
J1 -- BANANA JACK J2 -J4 -- 0.5 INCH JUMPERS S1 -- 25-PIN D CONNECTOR (AMP #747469-4) R1 -- 49.9K R2 -- 2KOHM TRIMPOT R3 -- 1.5KOHM R4 -- 1.5KOHM R5 -- 3KOHM R6, R7, R8 -- 10KOHM
U4D
GCLK
SP9841.BAS 'This program accepts an address (1 through 8) and data (0 through 255) 'in decimal and sends them to the DAC. Addresses 1 through 8 will 'correspond to converters A through H respectively. The appropriate 'output will be: Vout-(data/128)*VREF volts. 'We found that for our IBM PC/AT the LPT1 port address was 378H (Data 'Register 378H and control register 37AH) while for our IBM PC/XT the 'LPT1 port address was 3BCH (Data Register #BCH and control register 3BEH). DIM DIM DIM DIM DIM CLS lsb AS INTEGER msb AS INTEGER datareg AS INTEGER contrlreg AS INTEGER n AS INTEGER DO INPUT "Enter type of PC, AT or XT: ", type$ IN UCASE$(type$) = "AT" OR UCASE$(type$) = "XT" THEN EXIT DO ELSE PRINT "Please enter either AT or XT.": PRINT END IF LOOP IF UCASE$(type$) = "AT" THEN datareg = &H378: cntrlreg = &H37A IF UCASE$(type$) = "XT" THEN datareg = &H3BC: cntrlreg = &H3BE CLS n=0 DO WHILE n=0 DO test$ ="" INPUT "Enter Address (1 through 8): ", lsb IF lsb < 1 or lsb> 8 THEN test$ = "false" IF test$ = "false" THEN PRINT "Please enter a valid address.": PRINT LOOP UNTIL test$ <> "false" DO test$ = "" PRINT INPUT IF msb < 0 IF test$ = LOOP UNTIL
"Enter Data (0 through 255 in decimal): ", msb or msb > 255 THEN test$ = "false" "false" THEN PRINT "Please enter valid data.": PRINT test$ <> "false" 'set both latch clocks low 'send most significant byte to port 'clock U1 'send least significant byte to port 'clock U2 'enable U7, set U1 & U2 to serial out mode
OUT cntrlreg, $H3 OUT datareg, &H0 + msb OUT cntrlreg, &H2 OUT datareg, &H0 + lsb OUT cntrlreg, &H0 OUT cntrlreg, &H4 PRINT :
PRINT "Strike spacebar to enter new data or Q to quit." DO X$ = INKEY$ IF UCASE$(X$) = "Q" THEN n=1 LOOP UNTIL X$ = " " OR UCASE$(X$) = "Q"
LOOP END
Figure 16. Microsoft qbasic Program to Load Evaluation Board with Desired Codes.
297
ORDERING INFORMATION
Model SP9841KN SP9841KS SP9842KS SP9841BN SP9841BS SP9842BS Reference Inputs Temperature Range Package ................................... Eight, independent ................................................... 0 to + 70C .............................. 24-pin, 0.3" Plastic DIP ................................... Eight, independent ................................................... 0 to + 70C ........................................ 24-pin, 0.3" SOIC ................................... Four pair ................................................................... 0 to + 70C ........................................ 20-pin, 0.3" SOIC ................................... Eight, independent ............................................... -40 to + 85C .............................. 24-pin Plastic, 0.3" DIP ................................... Eight, independent ............................................... -40 to + 85C ........................................ 24-pin, 0.3" SOIC ................................... Four pair ............................................................... -40 to + 85C ........................................ 20-pin, 0.3" SOIC
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